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April 1996
NDP6060L / NDB6060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
Features
48A, 60V. R DS(ON) = 0.025 ? @ V GS = 5V.
Low drive requirements allowing operation directly from logic
drivers. V GS(TH) < 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R DS(ON) .
TO-220 and TO-263 (D 2 PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
T C = 25°C unless otherwise noted
Symbol
V DSS
V DGR
V GSS
Parameter
Drain-Source Voltage
Drain-Gate Voltage (R GS < 1 M ? )
Gate-Source Voltage - Continuous
NDP6060L
60
60
± 16
NDB6060L
Units
V
V
V
- Nonrepetitive (t P < 50 μs)
± 25
I D
Drain Current
- Continuous
48
A
- Pulsed
144
P D
T J ,T STG
T L
Total Power Dissipation @ T C = 25 ° C
Derate above 25 ° C
Operating and Storage Temperature
Maximum lead temperature for soldering
100
0.67
-65 to 175
275
W
W/ ° C
°C
°C
purposes, 1/8" from case for 5 seconds
? 1997 Fairchild Semiconductor Corporation
NDP6060L Rev. D / NDB6060L Rev. E
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